数字IC设计资料(IC前端|FPGA|ASIC) 今日: 0|主题: 26586|排名: 2

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[资料] [ebook]Soft Errors in Modern Electronic Systems ...2 3	pipiw 2010-10-12	218142	fireheart 2025-8-15 19:06
[资料] DMA在微处理器中的应用与设计 ...2	onearangel 2014-7-12	186693	snq31418 2025-8-15 18:49
[资料] cadence+synopsys license 大全 ...2 3 4 5 6..8	taku2006 2013-3-6	7927087	lida123456 2025-8-15 18:48
[资料] Synopsys的license生成器 ...2 3 4	kaprix 2010-5-19	3013376	lida123456 2025-8-15 18:47
[资料] 编码的奥秘-隐匿在计算机背后的软硬件语言(中文版) ...2	ZhengQC 2025-5-9	10872	beckwang1116 2025-8-15 17:43
[资料] Xilinx FPGA设计权威指南 Vivado集成设计环境 ...2 3 4 5 6..9	machaokuku 2019-7-16	8529438	yuduqjy 2025-8-15 14:44
accellera systemverilog workshop ...2 3	clarkkevin 2008-10-3	215408	blitzade 2025-8-15 10:48
[资料] 28nm_Timing_Signoff_Guidelines ...2 3 4 5	dboyman 2015-12-31	4612658	blitzade 2025-8-15 10:44
[资料] Design and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures @2020 ...2 3	2046 2022-11-6	235460	jimcmwang 2025-8-15 00:49
[原创] 《Synthesis of Finite State Machines Logic Optimization》 ...2 3 4	pwang7 2021-11-8	349947	jimcmwang 2025-8-15 00:40
[原创] 《Synthesis of Finite State Machines Functional Optimization》 ...2 3	pwang7 2021-11-8	299606	jimcmwang 2025-8-15 00:25
[资料] verilog 电子书40本打包下载，总有一本适合你有源码 ...2 3 4 5 6..106	megaic 2016-5-7	1056156094	yejingxiaozi 2025-8-14 21:17
[资料] 2014spyglass CDC 培训讲义 ...2 3 4 5 6..36	aurora9325 2014-4-24	35789021	saravanany5k 2025-8-14 20:52
[原创] Prime Time User Guide：2016版本 ...2 3 4 5 6..14	踏燕马 2016-6-17	13986849	saravanany5k 2025-8-14 20:44
asic design guide (600页，注册后才可下载) ...2 3 4 5 6..145	jackzhang 2003-7-17	1443183887	wangwd 2025-8-14 19:13
[资料] 非常好的DC （Design Compiler）学习资料 ...2 3 4 5 6..34	RainskyXiang 2010-10-2	33281123	andersondon 2025-8-14 18:44
[原创] 【数字集成电路设计与技术】(国家集成电路工程领域工程硕士系列教材) 清晰版 ...2 3 4 5 6..52	benemale 2010-6-16	51896860	jyuansea 2025-8-14 18:04
[资料] 《学习VI和VIM编辑器》第７版中文版 ...2 3 4 5 6..8	我没逗你玩儿 2016-3-20	7622520	Ralphjh 2025-8-14 15:34
[原创] samsung 最新 toggle 32GB MLC NAND Flash Datasheet ...2 3 4 5 6	xiaofeixia 2010-12-3	5117685	亦然韩冷 2025-8-14 14:32
[资料] 时序设计与约束资料汇总 ...2 3 4 5 6..11	ray21880 2018-9-19	10331520	chenqi1732 2025-8-14 10:43
[原创] 8-stage Deep-pipelined MIPS CPU(文档、rtl、testbench) ...2 3 4 5 6..7	xileito 2013-1-16	6616986	xileito 2025-8-14 07:30
[资料] Constraining Designs for Synthesis and Timing Analysis ...2 3 4 5 6..35	bingjunpeng 2013-7-13	34685992	saravanany5k2 2025-8-14 02:26
[原创] 直接产生verilog的testbench的python脚本精华3 ...2 3 4 5 6..19	haimag 2012-2-7	18189747	saravanany5k2 2025-8-14 02:21
[资料] IC芯片设计中的静态时序分析实践 ...2 3	ZhengQC 2025-5-9	211651	saravanany5k2 2025-8-14 02:07
TCL和Perl语言经典书籍大集合 ...2 3 4 5 6..18	duweiwei_lydia 2009-8-24	17046015	saravanany5k1 2025-8-14 01:56
[资料] DDR verilog RTL ...2	hqhjj 2011-10-23	196696	saravanany5k1 2025-8-14 01:54
[资料] ARM AMBA互联相关IP文档汇总（APB/AHB/AXI/ACE）	1806551899 2025-6-20	4747	saravanany5k 2025-8-14 01:19
[资料] Xilinx_zynq_book（中文版）+源码 ...2 3 4 5	DLjohn 2019-8-29	4715891	saravanany5k 2025-8-14 01:18
[资料] Advanced Encryption Standard (AES)	ZhengQC 2025-5-10	4613	saravanany5k 2025-8-14 01:14
[资料] Prime Time 2018 User_Guide ...2	ICer_hao 2024-3-7	152299	saravanany5k 2025-8-14 01:12
[资料] 数字设计:原理与实践(原书第4版) ...2 3	Cortex-M3 2013-5-2	207450	nanfengqingfu 2025-8-14 00:05
[资料] Synopsys 2018 System Verilog and UVM Lab files ...2 3 4	lianyi1990 2024-6-26	367019	电子悟空 2025-8-13 23:40
[资料] Xilinx Vitis Vivado Unified v2024.1 ...2 3	janetchin 2024-6-25	235275	jingjisong 2025-8-13 19:57
[资料] 同步复位，异步复位资料 ...2	ICer_hao 2024-3-7	111951	苍穹521earth 2025-8-13 18:00
[原创] AMBA® 3 AHB-Lite 协议中文版 ...2 3 4 5 6..86	尐翟 2020-9-8	856146831	chenqi1732 2025-8-13 17:54

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