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    <title>EETOP 创芯网论坛 (原名：电子顶级开发网) - Xilinx SDSoC免费license申请活动</title>
    <link>https://bbs.eetop.wang/forum-315-1.html</link>
    <description>Latest 20 threads of Xilinx SDSoC免费license申请活动</description>
    <copyright>Copyright(C) EETOP 创芯网论坛 (原名：电子顶级开发网)</copyright>
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      <title>EETOP 创芯网论坛 (原名：电子顶级开发网)</title>
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    <item>
      <title>Xilinx SDSoC免费license申请结果公布</title>
      <link>https://bbs.eetop.wang/thread-620151-1-1.html</link>
      <description><![CDATA[先和大家道个歉，本来这个活动的初衷是为大家申请到一个永久的Xilinx SDSoC免费license，但是可能是由于理解性的偏差，最后赛灵思美国总部那边给出的是一个评估版的License，而且在前几日已公布在了xilinx微信。

可以点击：申请License  获取

所以本次活动偏离了我们 ...]]></description>
      <category>Xilinx SDSoC免费license申请活动</category>
      <author>jackzhang</author>
      <pubDate>Mon, 26 Dec 2016 03:13:49 +0000</pubDate>
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    <item>
      <title>the clock of DDR3 has multiple driver(s)</title>
      <link>https://bbs.eetop.wang/thread-617677-1-1.html</link>
      <description><![CDATA[The design of the top is showing as follows. The software question is logical net \'CLK_OUT\' has multiple driver(s). How can I solve the problems ? Thanks  a lot.



module top(
    input clk,
    input rst,



inout[15:0] mcb3_dram_dq,     
]]></description>
      <category>Xilinx SDSoC免费license申请活动</category>
      <author>汉白雪玉</author>
      <pubDate>Sun, 13 Nov 2016 10:56:26 +0000</pubDate>
    </item>
    <item>
      <title>SDSoC（评估板）免费license申请活动（奖励信元）</title>
      <link>https://bbs.eetop.wang/thread-616103-1-1.html</link>
      <description><![CDATA[SDSoC简介SDSoC开发环境是赛灵思SDx?软件定义开发环境系列成员之一，包括扩展库、开发板、设计服务生态系统支持，可实现嵌入式C/C++语言应用开发。该SDSoC?开发环境正式版还强化了集成设计环境（IDE）的功能与特性，让编程和平台开发更加简便容易。活动规则及奖励：1.  ...]]></description>
      <category>Xilinx SDSoC免费license申请活动</category>
      <author>jackzhang</author>
      <pubDate>Thu, 20 Oct 2016 01:34:57 +0000</pubDate>
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