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    <title>EETOP 创芯网论坛 (原名：电子顶级开发网) - RISC-V 专区</title>
    <link>https://bbs.eetop.wang/forum-333-1.html</link>
    <description>Latest 20 threads of RISC-V 专区</description>
    <copyright>Copyright(C) EETOP 创芯网论坛 (原名：电子顶级开发网)</copyright>
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    <lastBuildDate>Sun, 07 Jun 2026 04:35:53 +0000</lastBuildDate>
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      <title>EETOP 创芯网论坛 (原名：电子顶级开发网)</title>
      <link>https://bbs.eetop.wang/</link>
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    <item>
      <title>求8bit pic mcu IP</title>
      <link>https://bbs.eetop.wang/thread-994837-1-1.html</link>
      <description><![CDATA[求8bit pic mcu IP


VX:z980134]]></description>
      <category>RISC-V 专区</category>
      <author>zjiankui</author>
      <pubDate>Sun, 07 Sep 2025 08:16:18 +0000</pubDate>
    </item>
    <item>
      <title>关于RISCV AMO指令的疑问</title>
      <link>https://bbs.eetop.wang/thread-991349-1-1.html</link>
      <description><![CDATA[以AMOSWAP指令为例，spec中给出实现锁的例子


上面这个例子里，程序认为AMOSWAP一定是原子的。但是对于AMOSWAP，一定是有一次LOAD和一次STORE，如何保证Load和store的原子性？尤其是如果使用axi4，不支持独占访问，感觉无法保证原子操作啊。
对比LR/SC，LR/SC是两条指 ...]]></description>
      <category>RISC-V 专区</category>
      <author>wenjohnny</author>
      <pubDate>Tue, 24 Jun 2025 09:50:49 +0000</pubDate>
    </item>
    <item>
      <title>Computer Architecture A Quantitative Approach Sixth Edition</title>
      <link>https://bbs.eetop.wang/thread-990513-1-1.html</link>
      <description><![CDATA[Computer Architecture A Quantitative Approach Sixth Edition]]></description>
      <category>RISC-V 专区</category>
      <author>ZhengQC</author>
      <pubDate>Mon, 09 Jun 2025 01:09:57 +0000</pubDate>
    </item>
    <item>
      <title>求个S家的sting工具</title>
      <link>https://bbs.eetop.wang/thread-990415-1-1.html</link>
      <description><![CDATA[如题：求个S家的sting工具]]></description>
      <category>RISC-V 专区</category>
      <author>george1977</author>
      <pubDate>Fri, 06 Jun 2025 06:42:53 +0000</pubDate>
    </item>
    <item>
      <title>CPU设计论文合集</title>
      <link>https://bbs.eetop.wang/thread-989314-1-1.html</link>
      <description><![CDATA[CPU设计论文合集]]></description>
      <category>RISC-V 专区</category>
      <author>ZhengQC</author>
      <pubDate>Wed, 14 May 2025 06:42:41 +0000</pubDate>
    </item>
    <item>
      <title>CMU 18-742 Lecture</title>
      <link>https://bbs.eetop.wang/thread-989311-1-1.html</link>
      <description><![CDATA[CMU 18-742 Lecture，Computer Architecture &amp; Systems]]></description>
      <category>RISC-V 专区</category>
      <author>ZhengQC</author>
      <pubDate>Wed, 14 May 2025 06:34:56 +0000</pubDate>
    </item>
    <item>
      <title>RISC-V Assembly Language Programming 2024</title>
      <link>https://bbs.eetop.wang/thread-989224-1-1.html</link>
      <description><![CDATA[RISC-V Assembly Language Programming - Unlock the Power of the RISC-V Instruction Set 2024



Gain the skills required to dive into the fundamentals of the RISC-V instruction set architecture. This book explains the basics of code optimization, as we]]></description>
      <category>RISC-V 专区</category>
      <author>post</author>
      <pubDate>Tue, 13 May 2025 05:29:11 +0000</pubDate>
    </item>
    <item>
      <title>RISC-V Assembly Language Programming - using ESP32-C3 and QEMU 2022</title>
      <link>https://bbs.eetop.wang/thread-989222-1-1.html</link>
      <description><![CDATA[RISC-V Assembly Language Programming: using ESP32-C3 and QEMU 2022

With the availability of free and open source C/C++ compilers today, you may wonder why someone might be interested in the assembly language. What is so appealing about the RISC-V (I ..]]></description>
      <category>RISC-V 专区</category>
      <author>post</author>
      <pubDate>Tue, 13 May 2025 05:08:41 +0000</pubDate>
    </item>
    <item>
      <title>Inside an Open-Source Processor - An Introduction to RISC-V 2021</title>
      <link>https://bbs.eetop.wang/thread-989218-1-1.html</link>
      <description><![CDATA[Inside an Open-Source Processor - An Introduction to RISC-V 2021

RISC-V is a free and open instruction set architecture (ISA). This means that ISA RISC-V itself does not require license fees, although individual implementations may charge. RISC-V IS ..]]></description>
      <category>RISC-V 专区</category>
      <author>post</author>
      <pubDate>Tue, 13 May 2025 03:27:16 +0000</pubDate>
    </item>
    <item>
      <title>Processor Microarchitecture: An Implementation Perspective</title>
      <link>https://bbs.eetop.wang/thread-989193-1-1.html</link>
      <description><![CDATA[分享CPU设计经典之作《Processor Microarchitecture: An Implementation Perspective》]]></description>
      <category>RISC-V 专区</category>
      <author>ZhengQC</author>
      <pubDate>Tue, 13 May 2025 00:32:38 +0000</pubDate>
    </item>
    <item>
      <title>Fundamentals of Superscalar Processors</title>
      <link>https://bbs.eetop.wang/thread-989192-1-1.html</link>
      <description><![CDATA[分享CPU书籍的经典之作《Fundamentals of Superscalar Processors》]]></description>
      <category>RISC-V 专区</category>
      <author>ZhengQC</author>
      <pubDate>Tue, 13 May 2025 00:31:08 +0000</pubDate>
    </item>
    <item>
      <title>CPU自制入门</title>
      <link>https://bbs.eetop.wang/thread-989191-1-1.html</link>
      <description><![CDATA[分享书籍《CPU自制入门》[图灵程序设计丛书]]]></description>
      <category>RISC-V 专区</category>
      <author>ZhengQC</author>
      <pubDate>Tue, 13 May 2025 00:30:05 +0000</pubDate>
    </item>
    <item>
      <title>计算机组成与设计：硬件软件接口 RISC-V版</title>
      <link>https://bbs.eetop.wang/thread-989190-1-1.html</link>
      <description><![CDATA[分享《计算机组成与设计：硬件软件接口 RISC-V版》]]></description>
      <category>RISC-V 专区</category>
      <author>ZhengQC</author>
      <pubDate>Tue, 13 May 2025 00:28:23 +0000</pubDate>
    </item>
    <item>
      <title>手把手教你设计CPU—RISC-V处理器篇 (胡振波) ，高清PDF，文字可复制，非影印版</title>
      <link>https://bbs.eetop.wang/thread-989188-1-1.html</link>
      <description><![CDATA[分享《手把手教你设计CPU—RISC-V处理器篇 (胡振波) 》，高清PDF，文字可复制，非影印版]]></description>
      <category>RISC-V 专区</category>
      <author>ZhengQC</author>
      <pubDate>Tue, 13 May 2025 00:23:13 +0000</pubDate>
    </item>
    <item>
      <title>分享两本学习SystemC的书籍</title>
      <link>https://bbs.eetop.wang/thread-989012-1-1.html</link>
      <description><![CDATA[分享两本学习SystemC的书籍：《System入门》、《SystemC片上系统设计》]]></description>
      <category>RISC-V 专区</category>
      <author>ZhengQC</author>
      <pubDate>Fri, 09 May 2025 08:24:40 +0000</pubDate>
    </item>
    <item>
      <title>求助riscv32-unknown-elf</title>
      <link>https://bbs.eetop.wang/thread-988655-1-1.html</link>
      <description><![CDATA[求助编译后的riscv32-unknown-elf-gcc和riscv32-unknown-elf-ld]]></description>
      <category>RISC-V 专区</category>
      <author>fengzhepianzhou</author>
      <pubDate>Thu, 01 May 2025 06:01:43 +0000</pubDate>
    </item>
    <item>
      <title>有做过openC910 综合和PR的吗?</title>
      <link>https://bbs.eetop.wang/thread-988045-1-1.html</link>
      <description><![CDATA[有做过 openC910 综合和PR 的吗？ sdc 和upf 要如何修改， floorplan 摆放有介绍的信息吗？ 

谢谢！]]></description>
      <category>RISC-V 专区</category>
      <author>fanghui_yang</author>
      <pubDate>Sun, 20 Apr 2025 08:33:19 +0000</pubDate>
    </item>
    <item>
      <title>cpu benchmark会验算结果吗？</title>
      <link>https://bbs.eetop.wang/thread-987528-1-1.html</link>
      <description><![CDATA[经常看到说cpu becnchmark跑分。我想知道如果1个cpu跑得快，但是它计算的结果是错的，这种情况在becnchmark怎么发现？]]></description>
      <category>RISC-V 专区</category>
      <author>zhangdeshuai</author>
      <pubDate>Thu, 10 Apr 2025 12:32:42 +0000</pubDate>
    </item>
    <item>
      <title>寻找项目合作伙伴或者合伙人</title>
      <link>https://bbs.eetop.wang/thread-986537-1-1.html</link>
      <description><![CDATA[我们团队主要从事众核芯片IP项目，产品有：1、RISCV CPU IP。包括其编译器、图形化IDE、在线调试等完整处理器工具链。支持多发射、多线程技术。2、NOC片上网络IP。基于目录协议支持cache一致性。有Icache/Dcache IP及片上多级cache系统，支持本地AMBA挂载。3、Verilog E ...]]></description>
      <category>RISC-V 专区</category>
      <author>lordprotector</author>
      <pubDate>Tue, 25 Mar 2025 01:29:18 +0000</pubDate>
    </item>
    <item>
      <title>icc数字后端</title>
      <link>https://bbs.eetop.wang/thread-986352-1-1.html</link>
      <description><![CDATA[这个怎么回事啊，macro没有放在规定区域里]]></description>
      <category>RISC-V 专区</category>
      <author>zhongjx23</author>
      <pubDate>Thu, 20 Mar 2025 09:17:23 +0000</pubDate>
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