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    <title>EETOP 创芯网论坛 (原名：电子顶级开发网) - 数字IC设计资料(IC前端|FPGA|ASIC)</title>
    <link>https://bbs.eetop.wang/forum-5-1.html</link>
    <description>Latest 20 threads of 数字IC设计资料(IC前端|FPGA|ASIC)</description>
    <copyright>Copyright(C) EETOP 创芯网论坛 (原名：电子顶级开发网)</copyright>
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      <title>EETOP 创芯网论坛 (原名：电子顶级开发网)</title>
      <link>https://bbs.eetop.wang/</link>
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    <item>
      <title>灵衢架构-资料</title>
      <link>https://bbs.eetop.wang/thread-995430-1-1.html</link>
      <description><![CDATA[]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>白无常</author>
      <pubDate>Sat, 20 Sep 2025 02:57:46 +0000</pubDate>
    </item>
    <item>
      <title>《芯片形式化验证》配套资料求助，需要solvnetplus账号下载</title>
      <link>https://bbs.eetop.wang/thread-995407-1-1.html</link>
      <description><![CDATA[]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>anatech</author>
      <pubDate>Fri, 19 Sep 2025 06:21:41 +0000</pubDate>
    </item>
    <item>
      <title>使用AHB dmac的关键问题详细解释</title>
      <link>https://bbs.eetop.wang/thread-995354-1-1.html</link>
      <description><![CDATA[1.谁作为流控制器（flow controller）  2.确定block大小  3. single burst数量]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>xf2016</author>
      <pubDate>Thu, 18 Sep 2025 06:43:36 +0000</pubDate>
    </item>
    <item>
      <title>数字电路基础</title>
      <link>https://bbs.eetop.wang/thread-995258-1-1.html</link>
      <description><![CDATA[]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>cai2010</author>
      <pubDate>Wed, 17 Sep 2025 01:25:23 +0000</pubDate>
    </item>
    <item>
      <title>Xilinx高性能NVMe Host控制器IP，4通道DMA，1通道IO，纯逻辑实现，AXI4和AXI4-Stream DMA接口，支持PCIe 3.0和PCIe 4.0</title>
      <link>https://bbs.eetop.wang/thread-995145-1-1.html</link>
      <description><![CDATA[NVMe AXI4 Host Controller IP1     介绍NVMe AXI4 Host Controller IP可以连接高速存储PCIe SSD，无需CPU，自动加速处理所有的NVMe协议命令，具备独立的数据写入和读取AXI4接口，不但适用高性能、顺序访问的应用，也适用于随机访问的应用，同时结合外部存储器（比如DDR ...]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>axpro</author>
      <pubDate>Sun, 14 Sep 2025 10:48:56 +0000</pubDate>
    </item>
    <item>
      <title>信息论与编码</title>
      <link>https://bbs.eetop.wang/thread-995063-1-1.html</link>
      <description><![CDATA[信息轮与编码]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>白无常</author>
      <pubDate>Thu, 11 Sep 2025 12:44:14 +0000</pubDate>
    </item>
    <item>
      <title>hifi4，功能兼容hifi3，欢迎交流</title>
      <link>https://bbs.eetop.wang/thread-994977-1-1.html</link>
      <description><![CDATA[hifi4，功能兼容hifi3，欢迎交流]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>fengchuibuluo</author>
      <pubDate>Wed, 10 Sep 2025 03:08:06 +0000</pubDate>
    </item>
    <item>
      <title>svliv v0.5</title>
      <link>https://bbs.eetop.wang/thread-994966-1-1.html</link>
      <description><![CDATA[]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>jacklog</author>
      <pubDate>Wed, 10 Sep 2025 01:42:29 +0000</pubDate>
    </item>
    <item>
      <title>inout 端口在穿过module时如何定义？</title>
      <link>https://bbs.eetop.wang/thread-994868-1-1.html</link>
      <description><![CDATA[求助～


有个inout A信号，需要穿过module，如下图所示：

A和B都是inout，中间没有做任何逻辑，单纯就是信号从module中穿过。

并且没有 表征输入/输入的选择信号，只有单独一根inout信号。

这种在 Verilog 中如何定义？


 ...]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>salfox</author>
      <pubDate>Mon, 08 Sep 2025 06:31:21 +0000</pubDate>
    </item>
    <item>
      <title>基于LZO的无损数据压缩IP，高性能版本，压缩速率32Gbps，适用于FPGA&amp;ASIC</title>
      <link>https://bbs.eetop.wang/thread-994847-1-1.html</link>
      <description><![CDATA[LZOAccel-CLZO Data Compression Core/无损数据压缩IP CoreLZOAccel-C是一个无损数据压缩引擎的FPGA硬件实现，兼容LZO 2.10标准。Core接收未压缩的输入数据块，产生压缩后的数据块。Core使用合适的头和尾封装了压缩后的数据载荷，所以用户不需要处理压缩后的数据块。输 ...]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>axpro</author>
      <pubDate>Sun, 07 Sep 2025 14:22:58 +0000</pubDate>
    </item>
    <item>
      <title>M_CAN ip资料，欢迎交流</title>
      <link>https://bbs.eetop.wang/thread-994836-1-1.html</link>
      <description><![CDATA[M_CAN ip资料，欢迎交流]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>fengchuibuluo</author>
      <pubDate>Sun, 07 Sep 2025 07:24:57 +0000</pubDate>
    </item>
    <item>
      <title>【部分学校指定教科书】数字集成电路：电路、系统与设计(第二版) 周润德</title>
      <link>https://bbs.eetop.wang/thread-994835-1-1.html</link>
      <description><![CDATA[数字集成电路：电路、系统与设计(第二版)]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>ICdesign101</author>
      <pubDate>Sun, 07 Sep 2025 06:47:04 +0000</pubDate>
    </item>
    <item>
      <title>数字IC设计入门</title>
      <link>https://bbs.eetop.wang/thread-994790-1-1.html</link>
      <description><![CDATA[]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>ryx1234560</author>
      <pubDate>Fri, 05 Sep 2025 14:45:29 +0000</pubDate>
    </item>
    <item>
      <title>ISSCC【2018-2024】最全论文资料合集 ——更新</title>
      <link>https://bbs.eetop.wang/thread-994681-1-1.html</link>
      <description><![CDATA[附件更新近8年最全的ISSCC论文合集，之前反馈失效，现在进行更新。

如失效 请私信我]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>SGF_learning</author>
      <pubDate>Thu, 04 Sep 2025 06:56:24 +0000</pubDate>
    </item>
    <item>
      <title>ONFI 5.2 SPEC</title>
      <link>https://bbs.eetop.wang/thread-994516-1-1.html</link>
      <description><![CDATA[ONFI 5.2 SPEC]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>juliuszwj</author>
      <pubDate>Mon, 01 Sep 2025 08:57:35 +0000</pubDate>
    </item>
    <item>
      <title>求dwc的Ethernet PCS Core文档</title>
      <link>https://bbs.eetop.wang/thread-994509-1-1.html</link>
      <description><![CDATA[求一份 400 Gigabit Ethernet PCS Core, Reference Guide, Version 2.7, Dec. 2021]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>creatingss</author>
      <pubDate>Mon, 01 Sep 2025 08:08:24 +0000</pubDate>
    </item>
    <item>
      <title>IC行业报告，值得一阅</title>
      <link>https://bbs.eetop.wang/thread-994394-1-1.html</link>
      <description><![CDATA[从《2023新型算力中心调研报告》看AI算力投资机会
**** 本内容被作者隐藏 ****]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>尐翟</author>
      <pubDate>Fri, 29 Aug 2025 11:30:07 +0000</pubDate>
    </item>
    <item>
      <title>Hotchips2025</title>
      <link>https://bbs.eetop.wang/thread-994304-1-1.html</link>
      <description><![CDATA[通过网盘分享的文件：
链接: 
**** 本内容被作者隐藏 ****


提取码: bach]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>looneyxp</author>
      <pubDate>Wed, 27 Aug 2025 15:10:41 +0000</pubDate>
    </item>
    <item>
      <title>计算机体系结构-量化研究方法（第6版）</title>
      <link>https://bbs.eetop.wang/thread-994231-1-1.html</link>
      <description><![CDATA[大师作品，体系结构权威经典教材，pdf 扫描版
来自 z-library]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>sung</author>
      <pubDate>Tue, 26 Aug 2025 07:43:19 +0000</pubDate>
    </item>
    <item>
      <title>ARM cortex-M0全可编程Soc原理及实现</title>
      <link>https://bbs.eetop.wang/thread-994156-1-1.html</link>
      <description><![CDATA[ARM cortex-M0全可编程Soc原理及实现 面向处理器、协议、外设、编程和操作系统]]></description>
      <category>数字IC设计资料(IC前端|FPGA|ASIC)</category>
      <author>liuyb</author>
      <pubDate>Mon, 25 Aug 2025 09:13:22 +0000</pubDate>
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