questions on verilog pipeline

sevid

hi,everyone
i have several questions about how to implement a pipeline with verilogHDL.

1. is the example below acts as a pipeline adder ?
module MY_CHIP(A, B, CIN, Clock_In, SUM, COUT);
   input CIN;
   input [7:0]A,B;
   input Clock_In;
   output [7:0]SUM;
   reg    [7:0]SUM;
   output COUT;
   reg    COUT;
   reg    [3:0]SUM1;
   reg    COUT1;
   always @(posedge Clock_In)
      begin
         {COUT1,SUM1} = A[3:0] + B[3:0] + CIN;
      end
   always @(posedge Clock_In)
      begin
         {COUT,SUM} = {A[7:4]+B[7:4]+COUT1,SUM1};
      end
endmodule



2. how to design a multi-level pipeline of many modules,e.g. 4 modules,with verilogHDL ?
    and if these modules have different clock cycles ?
    (and a simple question: how to find the number of clock cycle of one module ? )

a newer of pipeline field, pls give me some advise.
and thanks in advance !

Candydarte

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