急聘Staff Physical Verification Engineer 上海

cavell2010

Staff Physical Verification Engineer

Responsibilities:

Assist multiple Zoran design groups in physical verification (DRC/LVS/ERC/Antenna), chip-level layout and tapeout reviews, as well as maintaining physical verification flow, layout and add-on tools. You also will take physical design (P&R) projects from time to time.

Qualifications:

Expert user of Cadence Virtusso, Laker or Mentor IC-Station.

Expert user of Mentor*s Calibre or Synopsys* Hercules runsets or ruledecks creation and debugging.

Must be programming-minded capable of writing Tcl or Perl.

In-depth understanding of fabrication processing steps used in major foundries.
Proven track records of working independently on running and debugging chip-level DRC/LVS/ERC/Antenna results.

Self-motivated team worker, good verbal and written communication skills.

Knowledge of Synopsys Place-and-Route tools

Must able to work under tapeout pressure and tight schedule

8+ years of direct experience on IC layout, physical verification and tapeout (MS 6+years)

工作地点：上海

公司性质：美资原厂

MSN：cavell2010@hotmail.com

IChina

It looks not bad

angel

It looks good, but very hard!

cavell2010

Maybe you can tell your friends about this position,thank you very much！