找回密码
 注册

手机号码,快捷登录

手机号码,快捷登录

查看: 1930|回复: 0

[招聘] MTK北京招聘Senior design verification methodology engineer

[复制链接]
发表于 2011-9-6 22:44:15 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

×
Job Title: Senior design verification methodology engineer  
Location: Beijing  
Job description:  
1. Setup advanced ASIC design verification methodology/working flow.  
2. Apply advanced verification methodology to complex module/sub-system verification.  
3. Keep in touch with  EDA vendors to keep the leading position of design verification methodology.      
4. Company common verification infrastructure setup and maintain.      
   
Requirement:  
1. Ms Degree in Microelectronics/Electrical Engineering/Computer Science.  
2. Minimum 1 years of ASIC design/verification experience.      
3. Familiar with one of Contraint Random Verification(CRV) methodologies - VMM/OVM/UVM.  
4. Familiar with perl and tcl script.  
5. Familiar with SOC architecture and AMBA specification is a plus.  
6. Experience of one of the following field is highly preferred.
    -> Complex VIP development with VMM/OVM/UVM.  
    -> Low power verification techniques
    -> SystemC design verification and SC/SV co-simulation.
    -> Hardware acceleration technique.
    -> Complex IP verification experience, like PCIE,USB3.
  
Please send your resume to tao.liu@mediatek.com if you're interested.
您需要登录后才可以回帖 登录 | 注册

本版积分规则

QQ|手机版|小黑屋|关于我们|联系我们|隐私声明|EETOP 创芯网 ( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2026-1-15 22:44 , Processed in 0.030310 second(s), 6 queries , Gzip On, Redis On.

Powered by Discuz! X3.5

© 2001-2026 Discuz! Team.

快速回复 返回顶部 返回列表