招Senior mixed signal verification designer

judy102

Senior mixed signal verification designer

Education:    MS or above in Electrical / Electronic Engineering.

Experience:

        Master with 4+ experience with emphasis in mixed-signal, digital integrated circuit design.
        Familiar with Verilog coding, digital verification, mixed signal verification and the use of various design CAD tools such as VCS, NC-Verilog, HSPICE, Spectre,  etc.
        Familiar with SOC chips, knowledge of memory, PLL, ADC, DAC is preferred.

Requirements:           

Description of Function & Responsibility         

        Design digital behavior model for SOC analog IP, such as transceiver, PLL, high speed SERDES, etc.
        Build simulation environment to verify digital behavior model.
        Build mixed signal simulation environment to do Verilog-Spice verification. Check mixed signal simulation results with behavior simulation results to correct model.
        Extract analog IP timing information and verify.



Interested individual please contact with Judy for further confidential discussion via:
Tel: +86(21)61023600 * 858
MSN: lily.12120@hotmail.com

* Your private information will be treated in strict confidence and used only for recruitment purpose. Thanks.