formality undriven signal cut-point

henry_wangjj

Hi, all

plz help with the following formality troubles

In my design, I have some empty ports(which are finally not used, and are kept given the current project stage),

however when doing formal-check(REF: synthesis netlist, IMP: route netlist), troubles are issued.

eg. the empty port "PORT_0" are matched point and are verified, however the following unmatched points are issued

Ref Und REF:/WORK/design/PORT_O(1 reference, 0 implementation)

do I need to care this, or how to fix it?
thanks in advance

regards,
henry