高薪 急聘资深ASIC/FPGA Design 0r Verification Enginee

MerryLong

高薪 急聘

（1）Senior ASIC /FPGA Design Engineer

要求：

·Completed MultipleASICs or Xilinx/Altera(Virtex/ Stratix) FPGA designs

·Design cycle competence from architectural specificationdefinition, Verilog coding, synthesis and timing closure to post-silicon debug and support in a lab environment *Strong experiencein FPGA and ASIC design environments where FPGA code development ports to ASICs for production

·Strong verification with SystemVerilog, VMM/OVM/UVM.Expert in Verilog/VHDL, System Verilog and C

·Experience with OTN, Sonet,Ethernet, Packet Switching
        ·High-speed interfaceexperience - i.e. SATA, SAS, PCIe, Fibre Channel,etc

·Memory systems and Memory controller experience(i.e. DDR2, 3, etc.)

·SOC Architecturedesign and implementation knowledge.

·Scripting language experience (i.e. Perl, Shell, Pytho

·ECC (error correction code) & data compressionalgorithm experience

·HW behavioural modeling in SystemC, C/C++

·Excellent verbal and written communication skills

·Ability to work in a team environment

     (2)Senior FPGA Verification Engineer

要求：

      Good Knowledge on FPGA design process, procedure, knowledge on verification methodology, OVM is a plus
      Familiar with Verilog and SystemVerilog, VHDL isa plus.

      SystemVerilog and OVM(VMMor UVM) are needed skills for our verification engineers

工作地点：北京/上海
有意者可将简历投往该邮箱：Merry.Long@cn.flextronics.com
联系方式：18221687238
长期有效