#set power analysis mode
set power_enable_analysis true
set power_analysis_mode averaged
#read and link the gatelevel netlist
set search_path "/home/IC/project/dc/LFinter/rtl "
set search_path "/home/IC/project/DC/Magicinter-dc/WORK"
set target_library "/home/IC/project/pr_lib_new/Target_lib/scc035ume_hd_rvt_ss_v3p0_125c.db /home/IC/project/pr_lib_new/Target_lib/scc035ume_hd_rvt_ff_v3p6_-40c.db"
set link_library "* $target_library"
read_verilog "/home/IC/project/PR/Inter_Chip_1/gcdGCDUnit_rtl.output.v"
set top_name Top
current_design TOP
link
#read sdc and set transition time
read_sdc "/home/IC/project/PR/Inter_Chip_1/gcdGCDUnit_rtl.output.sdc"
#check, update or report timing
check_timing
#read switching activity file
read_vcd "/home/IC/project/tapout2019/mssim/Inter_Chip_rp/Tb.vcd"
#check /report power
check_power
report_power -hierarchy