Ncverilog 仿RTL code时 加unit Delay

jiaoxin12366

ex：wire a, b;
assign b = a;
怎样能看到b 和a timing difference

ex：
input [7:0] addr;
input clk;
reg [7:0] addr_syn;
always @ (posedge clk)
addr_syn <= addr;
怎样能看到 addr_syn 的delay？

jiaoxin12366

求助......