vcs function coverage

萝小小卜

最近学习system Verilog，写了一个简单的addr对它做function coverage，但是得到的coverage结果都为0，代码如下，cov.sample得到的结果是 然后get_coverage的结果为

                               
登录/注册后可看大图

我用来两千次约束，get_coverage的结果应该至少是90%，但是我现在得到的结果为0.


`timescale 1ns/1ns

program automatic test(addr_io aio);


bit [2:0] a,b;

bit sum,cout;

bit [3:0] data;


class Transaction;

rand bit [2:0] a;

rand bit [2:0] b;

endclass


Transaction tr;


covergroup Coverage;

cv_a:coverpoint tr.a{bins a[]={[0:3]};}

    cv_b:coverpoint tr.b{bins b[]={[0:3]};}

    cv_sum:coverpoint sum{bins sum[]={[0:1]};}

    cv_cout:coverpoint cout{bins cout[]={[0:1]};}

    cv_data:coverpoint data{bins odata[]={[0:8]};}


    cross a,b,sum,cout,data;

    option.per_instance=1;

    option.goal=100;


endgroup:Coverage

Coverage cov;


real coverage;

initial begin

cov=new();

send();

cov.sample();

end


task send();

begin

aio.cb.rst_n<=0;

##2 aio.cb.rst_n<=1;

repeat(2000) begin

@aio.cb;

tr=new();

assert (tr.randomize());

$display("%t:Coverage total coverage is %f",$time,cov.get_coverage());

$display("a=%h b=%h",tr.a,tr.b);

end

end

endtask

endprogram

kuolifeng

cov.sample() 應該要在 tr.randomize() 後

idealm

你随机了2000次，但是只采样了一次