[NVIDIA英伟达] 热招 Mask Design Engineer -上海

NVHR

NVIDIA热招 Mask Design Engineer -上海

简历投递: tracyw@nvidia.com  微信: 1751315121

全员持股+周末双休+965+补充公积金+补充商业医疗保险

职位关键词: IP Layout

Job Description

We are now looking forMask Design Engineer for Digital IP team. The team develops the highperformance digital IPs used in our chips. The main role is layout design forSRAM, ROM and STDcell using the most advanced IC process in the world.

What you’ll be doing:

Develop digital IPlayouts with excellent PPA in the most advanced process node

Verify the layout incell level and macro level

Maintain the layoutsper requests from circuit designers or other internal customers

Create tools orscripts to improve work efficiency

What we need to see:

BS/MS in EE orequivalent experience

Fundamental knowledgein digital logic, semiconductor device and manufacturing process

Minimum 1 yearsworking experience on digital or mixed-signal layout design

Familiar with Cadencedesign environment and ICV/Calibre verification tools

Excellentcommunication in English

Ways to stand out fromthe crowd:

Experience on StandardCell or SRAM layout design

Experience on layoutdesign in 16/14nm node and beyond

Knowledge in place androute

Proficient user ofSkill or Perl

We are an equalopportunity employer and value diversity at our company. We do not discriminateon the basis of race, religion, color, national origin, gender, sexualorientation, age, marital status, veteran status, or disability status.