[NVIDIA英伟达]招聘DFT Engineer-上海

NVHR

NVIDIA热招 DFT Engineer-上海

简历投递: tracyw@nvidia.com  微信: 1751315121

全员持股+周末双休+965+补充公积金+补充商业医疗保险

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

What you’ll be doing:
You'll be responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog, MBIST, Scan, etc. You'll have chance to take the lead role for DFT verifications and bringup.
In long term, you can be a DFT lead for verification or extend the expertise to DFT design or methodology.
What we need to see:
BSEE with 3+, MSEE with 2+ years of experience or PhD or equivalent working experience in DFT or design verification.
Good understanding on ASIC design and verification.
Hands on experience on at least one DFT feature: Boundary Scan, 1500, MBIST, Scan, ATPG.
Experience in silicon debug and bring-up on the ATE is a plus.
Good exposure to clock design, timing/STA, place-n-route or power is a plus.
Excellent analytical skills in verification and debug.
Strong programming and scripting skills in Perl, Python or Tcl desired.
Excellent written and oral communication skills in English with the curiosity to work on challenges.