上海深圳招聘封装设计工程师

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手上有数十家IC设计公司的职位， 职位包括不限于IC架构/    数字设计/   模拟设计/   数字验证 /芯片验证  /后端  等等各类职位

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以下是2家公司的职位 ，薪水可以open

Package Design Engineer
工作职责
? 封装方案评估:
封装类型(FCBGA, MCM, CoWoS, 3D), 封装尺寸(≥50*50mm), 封装高度, 散热片选择，Decap方案等；
? C4 Bump方案 & Interposer方案：
C4 bump pattern设计，bump pitch, power/ground domain设计，Interposer方案实现性，评估C4 与uBump以及BGA pinmap可实现性；
? Substrate方案评估：
Substrate结构 (eg: 20Layer 9/2/9); Substrate叠层定义: 信号/电源/地，与SI&PI工程师合作分析，参考OSAT design rule进行Substrate 高速信号预设计&Power/Ground设计；
? Pinmap设计：
根据硬件接口框图，uBump & C4 bump pattern等信息，进行pinmap设计并优化；
? 封装BOM设计：
选择合适的封装和基板材料，协助SI&PI&Thermal等仿真分析；
? 封装制造：
选择合适的供应商，选择合适的Process flow，管理供应商进度、质量、良率、风险等；制定合理的DOE实验方案，分析实验结果，协助定位问题；
? 封装可靠性：
制定封装可靠性方案，分析实验结果，协助定位问题；
? 计划与质量：
制定封装设计工作计划，管控封装设计质量，Highlight封装环节风险与问题；

工作要求
? 了解Advanced 封装技术，例如FCBGA，2.5D， Fanout，具有3DIC知识者优先
? 具有大尺寸封装sign off经验者优先
? 自我激励，有与内部团队和外部团队合作，带领项目从构思到完成的经验
? 具有很强的学习能力，不断更新技术进度的潜力


芯片封装专家 上海 深圳
岗位描述
As a package designer, you will be responsible for advanced package design and technology development, as well as foundry management and vendor interfacing.

You responsibilities include, but not limited to:
Design rule development and implementation of in-house packaging layout to meet product requirements.
EDA tool set up and flow development.
PI/SI analysis on full chip and critical IPs at package and board level.
Define and develop package solution for high speed, high power and large pin count device in a cross-function team
Collaborate with foundry, PE, TE and QA teams on chip bring up and qualification.
Interface with vendors on process optimization, chip characterization and failure analysis for volume production
Drive new technology development such as multi-die, hybrid-bonding, advanced substrate, design for manufacturability and design for reliability, as a collaborative effort with vendors
岗位要求
Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of experience.
Hands on experiences the following: Cadence Allegro APD & SiP tools, Sigrity XtractIM, PowerSI
Hands on experiences with layout of FCBGA, MCM, SiP, W