Formality ERROR: FM-089

一颗菜芯

读入参考设计
read_verilog -r ./source/$active_design.v
No target library specified, default is WORK
Initializing DesignWare ...
Initialization Complete
Loading verilog file '/home/source/LQF_TOP_PAD.v'
Current container set to 'r'

read_vhdl -r ./source/UART_RX.vhd
No target library specified, default is WORK
Loading vhdl file '/home/lk/FM_LDPC/source/UART_RX.vhd'
Warning: /home/lk/FM_LDPC/source/UART_RX.vhd  line 55
        signal r_RX_Data_R block UART_RX.Behavioral
        Default initial value of signal will be ignored  (FMR_VHDL-1002)
Warning: /home/lk/FM_LDPC/source/UART_RX.vhd  line 56
        signal r_RX_Data block UART_RX.Behavioral
        Default initial value of signal will be ignored  (FMR_VHDL-1002)
Warning: /home/lk/FM_LDPC/source/UART_RX.vhd  line 58
        signal r_Clk_Count block UART_RX.Behavioral
        Default initial value of signal will be ignored  (FMR_VHDL-1002)
Warning: /home/lk/FM_LDPC/source/UART_RX.vhd  line 59
        signal r_Bit_Index block UART_RX.Behavioral
        Default initial value of signal will be ignored  (FMR_VHDL-1002)
Warning: /home/lk/FM_LDPC/source/UART_RX.vhd  line 60
        signal r_RX_Byte block UART_RX.Behavioral
        Default initial value of signal will be ignored  (FMR_VHDL-1002)
Warning: /home/lk/FM_LDPC/source/UART_RX.vhd  line 61
        signal r_RX_DV block UART_RX.Behavioral
        Default initial value of signal will be ignored  (FMR_VHDL-1002)
Error: RTL interpretation messages were produced during read.
        Verification results may disagree with a logic simulator. (FM-089)
0
尝试了set_mismatch_message_filter  -warn  FM-089 还是会报错，有大佬知道如何解决吗