ASIC 时钟mux约束

玉林枫

各位大侠，请问下面这种情况该如何约束？

#源时钟定义

create_clock –name clk1 –period <> [get_portsclk1]

create_clock –name clk2 –period <> [get_portsclk2]

create_clock –name clk3 –period <> [get_portsclk3]

set_clock_groups –logically_exclusive –group{ clk_mux1_1} –group { clk_mux1_2} –group { clk_mux1_3}

#FFdiv1生成时钟定义

create_generate_clock –name clk_div_1 –divide_by2 –source [get_pins FFDdiv1_ck] –master_clock [get_clocks clk1] [get_pins FFDdiv1_q]

create_generate_clock –name clk_div_2 –divide_by2 –source [get_pins FFDdiv1_ck] –master_clock [get_clocks clk2] [get_pins FFDdiv1_q]–add

create_generate_clock –name clk_div_3 –divide_by2 –source [get_pins FFDdiv1_ck] –master_clock [get_clocks clk3] [get_pins FFDdiv1_q]–add

set_clock_groups –physically_exclusive –group{ clk_div_1} –group { clk_div_2} –group { clk_div_3}

#FFdiv2 FFdiv3生成时钟如何定义，特别是master_clock怎么设置？

玉林枫

或者是这样的思路，mux1输出定义3个时钟，DDdiv1输出定义3个时钟，mux2输出定义3+3=6个时钟，FFdiv2输出定义6个时钟，FFdiv3输出定义6个时钟？