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Synopsys 新思科技武汉招聘数字验证工程师!
如有意向,请发简历至:Xuan.qin@synopsys.com; 注明“eetop+verification”
As a member of the Synopsys mixed signal IP team you will work with global teams to define and develop testplan, testbench and testcases to verify mixed signal (digital and analog) designs.
Position Responsibilities:
- Develop customer-facing testbench and tests.
- Integrate the testbench in an in-house release tool/infrastructure with customer-friendly interface to improve customer user experiences.
- Generates verification specifications.
- Determines test bench design and test cases.
- Evaluates and exercises various aspects of the development flow which may include items such as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, gate-level simulation and verification coverage metrics.
- Generates documentation for test plans, verification environments, and usage guide.
- Participate in evaluation, troubleshooting and debug of digital and mixed signal designs. |
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