Cadence: Verilog-XL Reference

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Cadence: Verilog-XL Reference
Contents
1. Introduction   . . . . . . . . . . . . . . . . . . ........18
2. Lexical Conventions . . . . . . . . . . . . . . .  .....22
3. Data Types. . . . . . . . . . . . . . . . . . . . ........ 30
4. Expressions  . . . . . . . . . . . . . . . . . . . ........50
5. Assignments. . . . . . . . . . . . . . . . . . . ........ 70
6. Gate and Switch Level Modeling. . . . . . . . . . .96
7. User-Defined Primitives (UDPs) . . . . . . . . . . 141
8. Behavioral Modeling. . . . . . . . . . . . . . . . .....161
9. Tasks and Functions . . . . . . . . . . . . . . ..... 194
10. Disabling of Named Blocks and Tasks . . . . .202
11. Hierarchical Structures. . . . . . . . . . . . ...... 206
12. Using Specify Blocks and Path Delays. . .  .  234
13. Timing Checks . . . . . . . . . . . . . . . . . . .....285
14. System Tasks and Functions. . . . . . . . . .  319
15. Programmable Logic Arrays . . . . . . . . . . . 394
16. Interconnect Delays . . . . . . . . . . . . . ..... .411
17. Timescales . . . . . . . . . . . . . . . . . ......... . 429
18. Delay Mode Selection . . . . . . . . . . . . ....   443
19.The Behavior Profiler . . . . . . . . . . . . ..... .  454
20. The Value Change Dump File. . . . . . . .. .. . 481

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