请yinchyang 等高手再解答我两个个问题，谢谢^_^

quxunzheng

自己已经搞懂了。。。

yinchyang

hehe
In verilog, my suggestion is to treat veriable as signal vector,
although the syntax of verilog and C is almost the same, they express different things.
I think , inverilog
tempreg means at least one signal in the vector is not zero.
If we treat it as a integer, maybe we will get confusion.