高薪诚聘 FPGA Verification Engineer

MerryLong

高薪 诚聘
FPGA Verification Engineer

要求：

            Good Knowledge on FPGA design process, procedure, knowledge on verification methodology, OVM is a plus
            Familiar with Verilog and SystemVerilog, VHDL isa plus.

            SystemVerilog and OVM(VMMor UVM) are needed skills for our verification engineers

工作地点：北京/上海
有意者可将简历投往该邮箱：Merry.Long@cn.flextronics.com
联系方式：18221687238
长期有效

thyears

ASIC的吧？怎么是FPGA的呢？

MerryLong

回复 2# thyears


    你好，ASIC和FPGA我们都需要的！