teramax atpg 能否生成最小完备测试集

hurrywork

能不能，怎么做呢，求助大佬

ip_qq3010583137

可以啊

hurrywork

回复 2# ip_qq3010583137


   请教一下大佬，具体的步骤怎么操作呢？目前知道的流程是：代码上要写入扫描链的端口，dc的脚本生成spf文件，teramax里导入spf，网表和verilog，这样就可以生成了吗，目前生成出来的测试向量：pattern group_ALL ("clk", "reset", "SCAN_TEST", "SCAN_CLK", "SCAN_ENA", "PIN_SI",
   "d", "PIN_SO", "pulse")
   { test_setup }
   vector("_default_WFT_")                 := [ X X 1 0 X X X X X ];
   vector("_default_WFT_")                 := [ X 1 1 0 X X X X X ];
   { non_scan_test }
   { pattern 0 parallel_clock basic_scan }
   { multiclock_capture }
   vector("_multiclock_capture_WFT_")      := [ 0 0 1 1 1 0 Z Z Z ];
end

有点奇怪，可能错了
verilog：
`timescale 1ns / 1ps
module count(clk,reset,d,

SCAN_TEST,
                SCAN_CLK,
                SCAN_ENA,
                PIN_SI,
                PIN_SO,
                pulse
  );
input clk,reset;
output d;
input SCAN_TEST,SCAN_CLK,SCAN_ENA,PIN_SI;
output PIN_SO,pulse;
reg d;
always@( posedge clk or posedge reset )begin
if(reset) d<=0;
else d<=1;
end
endmodule





dc的脚本：
#################################################################
# Synopsys DC script
#################################################################

#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# DC setup
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
#source library_setup.tcl
#source common_setup.tcl
set_app_var search_path          [list /usr/synopsys/dc2015/libraries/syn/smic18_digital_lib/smic_libv21/STD/Synopsys\
                                  /usr/synopsys/dc2015/libraries/syn/smic18_digital_lib/smic_libv21/STD/Symbol/synopsys]
set_app_var target_library  {smic18_ff.db}
set_app_var link_library    {smic18_ff.db smic18_ss.db }
set_app_var symbol_library  {/usr/synopsys/TetraMax2009/librarydownload/smic18_digital_lib/smic_libv21/STD/Symbol/synopsys/smic18.sdb}
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Analyze & elaborate RTL source
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
read_file -format verilog /workspace/2018_workspace/dc_test/yu/tmax_atpg/count.v
current_design count
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Link design
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
link

#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Check design
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
check_design

#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Apply constraints
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
set auto_wire_load_selection true
#set_max_area 1500000
set_max_fanout 16 [get_designs *]
set_max_capacitance 2 [get_designs *]
set_load 0.1  [get_nets * ]
set_load 50   [all_outputs]
set bind_unused_hierarchical_pins true

current_design count

create_clock -name "Fun_CLK" -period 20 -waveform { 0.000 10.000  }  { clk  }

set_dont_touch_network clk


#******************************* insert scan **************************************
compile
set_scan_configuration -style multiplexed_flip_flop
set_scan_configuration -clock_mixing no_mix
set_scan_configuration -internal_clocks single
set_dft_signal -view spec -type scanenable -active 1 -port SCAN_ENA
set_dft_signal -view spec -type testmode -active 1 -port SCAN_TEST
set_dft_signal -view existing_dft -type TestMode    -port SCAN_TEST  -active_state 1
set_dft_signal -view existing_dft -type Reset       -port reset      -active_state 0
set_dft_signal -view existing_dft -type ScanClock   -port SCAN_CLK   -timing {45 55}
set_dft_signal -view existing_dft -type ScanEnable  -port SCAN_ENA   -active_state 1
set_dft_signal -view spec         -type ScanDataIn  -port PIN_SI
set_dft_signal -view spec         -type ScanDataOut -port PIN_SO     
set_scan_configuration -chain_count 1
set_scan_path -view spec c0 -scan_data_in PIN_SI -scan_data_out PIN_SO

set_autofix_configuration -type clock -control_signal SCAN_TEST -test_data PIN_SI
set_autofix_configuration -type reset -control_signal SCAN_TEST -test_data PIN_SO
#compile -scan

create_test_protocol
# -capture_procedure multi_clock
preview_dft
insert_dft
#report_constraint -all_violators
#report_scan_path
dft_drc -verbose -coverage_estimate
write_test_protocol  -output /workspace/2018_workspace/dc_test/yu/tmax_atpg/count.spf

#*********************** * end insert scan  *****************************
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Uniquify
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
uniquify

#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Pass0 compile
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
compile_ultra

#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Report timing & area
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Write out netlist
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
change_names -rules verilog -hier
write -format verilog -hierarchy count  -output /workspace/2018_workspace/dc_test/yu/tmax_atpg/count_netlist.v
#write -f verilog -hier -output  /workspace/2018_workspace/dc_test/yu/tmax_atpg/count.vnet
#write -f ddc -hier -output /workspace/shi/counter.ddc

hurrywork

顶起来

大帅哥1989

请问，最小完备测试集是什么东东？