【EETOP创芯人才网职位发布 新思半导体科技】上海 浦东 IP Subsystem Design an d AE

创芯讲堂运营

IP Subsystem Design an d AE18000-35000 RMB
职位描述
招聘人数：若干 到岗时间：不限 年龄要求：不限 性别要求：不限 婚况要求：不限语言要求： 英语

We’re looking for an IP Subsystem Design and Application Engineer to join the team. Does this sound like a good role for you?

This role involves developing and verifying integrated Interface IP Subsystems.  Additionally, you’d:

Create design and verification specifications

Determine architecture, logic, test bench designs, and test cases

Define module interfaces and formats

Evaluate and exercise various aspects of the development flow which may include such items as RTL development, functional simulation, constraint development, design for test logic, synthesis, timing and power analysis, and verification coverage metrics

Key Qualifications:

Bachelor’s and/or master’s degree in electrical and/or Electronic Engineering, Computer Engineering or Computer Science

Minimum 3 years of IP and/or ASIC Design/Verification/Applications experience required

Hands-on experience in RTL coding, verification, synthesis, static timing analysis, equivalence check, etc.

Domain understanding of interface standards: PCIe, USB, Ethernet or DDR

Good communication skills while interacting with internal teams and customers

Preferred Experience:

Experience in Design Compiler, Fusion Compiler, Spyglass or VC

Experience in UVM methodology, DesignWare Cores, TCL, Perl, Python, or other shell scripting

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

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