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Job Responsibilities:
Work with designer to get a full deep insight on the design and develop stressful test plan
Build test bench and create testcase to ensure test coverage
Run simulation in both RTL and netlist level, debug and fix issues, create test reports
Run regression test for each design (RTL/Netlist) update
Develop verification IP which can be reused at different level verification
Co-work with FPGA engineer to prepare test vector, support test and debugJob Requirements
BS with 5+ years or MS with 3+ years of design verification experience.
Strong working knowledge in SystemVerilog, C and UVM, experienced in DPI integration
Experienced in building test benches, checkers, test vectors, assertions, coverage analysis
Experienced in SoC verification and debug, be familiar with AMBA protocol
Strong communications skill and capability
Self-motivated and good team player
Additional Preferred one or more of these Requirements:
Experience with software development practices including coding standards, code reviews, source control management, and continuous integration and testing
Strong Programming in Perl, Python
Good experience with commercial standard, like DDR,PCIE etc
联系方式:19926440332(微信同号)
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